Asic Design Companies
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The beginning of the ASIC can be traced back to the early 1980s. Around this time, ICs were beginning to make a major impact on the electronics industry. Some of the first attempts at trying to create a logic chips that could be focussed towards a specific application. One early initiative undertaken by Ferranti, a UK based company, used what was termed the uncommitted logic array (ULA). This scheme provided the customisation by varying the metal interconnect mask.
The first ULAs contained only a few thousand gates, but later versions had greater levels of flexibility and used different base dies customised by both metal and polysilicon layers. In some cases RAM elements were incorporated into the basic ULA.
From these early developments, a number of different types of ASIC have been developed. Now many ASIC design methodology are very complicated, and some are mixed signal ASICs that incorporate both analogue and digital circuitry.
Some of the major ASIC manufacturers are:
* Chartered * IBM * LSI Logic * SMIC * Texas Instruments * TSMC * UMC * Agere * Fujitsu * X-Fab
The development and manufacture of an ASIC design methodology is a very expensive process. In order to reduce the costs, there are different levels of customisation that can be used. The can enable costs to be reduced for designs where large levels of customisation of the ASIC are not required. Essentially there are three levels of ASIC that can be used:
* Gate Array This type of ASIC design methodology is the least customisable. Here the silicon layers are standard but the metallisation layers allowing the interconnections between different areas on the chip are customisable.
* Standard cell For this type of ASIC, the mask is a custom design, but the silicon is made up from library components. This gives a high degree of flexibility, provided that standard functions are able to meet the requirements.
* Full custom design This type of ASIC design methodology is the most flexible because it involves the design of the ASIC down to transistor level. While it gives the highest degree of flexibility, the costs are very much higher and it takes much longer to develop. The risks are also higher as the whole design is untested and not built up from library elements that have been used before.
The entire process for designing an Application Specific Integrated Circuit consists of the following steps:-
* Specification * Design * Simulate * Synthesize * Place and Route * Re-simulate * Chip Testing * Packaging
Specification: The specification serves as a guide for choosing the right ASIC technology and helps the vendor know your needs. Further a specification enables an engineer to understand the entire design or his part of the design (in the case of a large scale IC). Besides this the engineer can plan the correct interface to the rest of the pieces of the chip or to the system for which the ASIC is being developed. A specification should also include information like the major functional sections, description of the I/O pins, estimated gate count, Target power consumption and the test requirements. This also involves decision about the synthesis software you will be using if you plan to design the ASIC with a hardware description language. Finally a decision is taken about whether the design entry method should be schematic (smaller chips) or it involves the usage of a hardware description language (HDL) such as Verilog or VHDL (larger chips).
Design: The Design stage forms the basis for analyzing the ASIC for criteria of performance and functionality. This stage employs a top-down approach and needs to be synchronous with the rest of the system for which the ASIC is being developed. Greater emphasis is placed on achieving the final design through predominant usage of the universal NAND gates while maintaining a check on the number of power and ground pins.
Simulate: Simulation process is done parallel to the design process.Small sections of the design are simulated separately and then connected to larger sections. Simulation is done repeatedly for each new designed section till the completion of the whole IC. This is done to ensure flawless functionality.
Synthesize: Synthesis stage is necessary if the design was entered using an HDL. This involves using synthesis software to optimally translate the register transfer level (RTL) design into a gate level design.
Place and Route: This stage determines the real layout of the ASIC. This step is typically done by engineers at the vendor*s facility, with input from the design engineer. This is because the vendor*s engineers have more knowledge about their semiconductor processes and about the layout tools.
Re-simulate (final review): After the placing and routing, the ASIC is simulated for a final time to check for proper functionality of the complete ASIC. In case of any deviation in the expected performance sections of the ASIC may need to be redesigned (if problems encountered are significant), re-synthesized with better constraints (if there are marginal timing paths or the design is slightly larger than the ASIC), or simply another place and route with better constraints. The final review confirms that nothing has been overlooked.
Chip Test: In the Testing stage the ASIC is subjected to a set of tests which include functional verification, performance verification and structural verification. ASIC test generation is mainly dependent on the device under test and may vary as it might contain the various circuit types like combinational circuits, synchronous sequential circuits, asynchronous circuits, memory array circuits or a combination of the above. Besides the presence of circuit types in the ASIC, the test generation is also based on the ASIC*s function, performance and structure. System integration and system testing is necessary at this point to insure that all parts of the system work correctly together.
Packaging: Packaging determines the number of I/Os, circuit power dissipation, amount of board space, etc., on the ASIC. The basic features of packaging are: 1) physical support and environmental protection for the die 2) weather proofing the die from the environment 3) heat dissipation from the die to the external atmosphere 4) maintaining the die's surface dry and inert 5) electrical connections between the die and the external circuitry
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