Asic Design Jobs
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ASIC ? Application specific Integrated Circuit: As the name specifies it?s an IC which is Application Specific. ASIC consists of large number of Gates. The ASICs which are now coming up in the industry not only include gates but also have 32 Bit processors ,Memory blocks like RAM, ROM, EEPROM. These ASIC are called as SOC (System- on- Chip). The Major ASIC manufacturers today in the market are IBM, LSI Logic, TSMC, and Texas Instruments. ASIC design flow has two parts. One is called as a logical design and other one is a Physical design. Floor planning, Placement, Routing, Extraction, and Post layout Simulation are some steps for Physical Design. Floor planning helps us to arrange the blocks over a chip,. It also helps us to decide about the location of I/O pads, and gives us an idea of choosing the type of power which should be distributed through the circuit. Floor planning helps is to minimize the floor chip area and minimizes the delay. After floor planning the next step is to do placement of the logic cells within the flexible blocks. Placement will help us in minimizing the cross talks between signals and power dissipation. Routing helps in making the connection between the cells and the blocks. Extraction in ASIC means the determination of the resistance and capacitance of the interconnect of cells and blocks. Post layout simulation is a kind of simulation which helps us to check the design works with added loads of interconnection.
A full custom design gives high performance and high design cost where as ASIC gives compromised performance with low cost. Example of a full custom design is a PC and workstation CPU, but ASIC is an I/O circuit or a DSP chip.
There are three kinds of ASIC. Full custom ASIC Semi custom ASIC and Programmable ASIC. Full Custom ASIC means that all the logic cells will be customized including the mask layers. It is the most expensive to manufacture and design. The manufacturing time is eight weeks. Semi custom ASIC is divided into Cell based ASIC, Gate Array based ASIC. Cell based ASIC are also called as Sea bick ASICs (CBIC). Manufacturing time for CBIC is at least eight weeks. These are built of rows of standard cells- like a wall built of bricks. Advantages of CBIC are it saves time, money and also reduces risk by using predesigned cell library. Features of CBIC are • All mask layers are customized. • Custom blocks can be embedded. Gate array based ASIC uses macros to reduce the turn around time. These arrays are comprised of a base array made of base cell. Gate array comprises of a Base Array. Base Array is manufactured by replicating the smallest element called as Base Cell. This array is often called as Masked Gate Array in order to separate it from other Gate arrays. There are 3 types of Gate Array ASIC: • Channeled Gate Array, • Channel less Array • Structured gate array. Channeled Gate Array has some important features. In this gate array only the interconnect is customized. Manufacturing lead time is somewhere between two days and two weeks. This array is very much similar to CBIC. Both these use rows of cells separated by channels. In channeled gate array the space for interconnect between the rows of cells are fixed in height whereas in CBIC it can be changed.
Channel less array is also called as channel free gate array, sea of gate array. The features of channel less array are: • Only few layers are customized. • Lead time for manufacturing is two days to two weeks. In channel less array there are no predefined areas set for routing between cells. It is routed over the top of gate array devices. The logic density is higher for these arrays.
Structured gate array is also called as embedded gate array. The important features of this type of array are: • Only the interconnection is customized. • Custom blocks can be embedded. • Lead time for manufacturing is two days to two weeks. Embedded gate array gives a improved area efficiency with a lower cost. The disadvantage of this type of array is that the embedded function is fixed.
Programmable ASIC?s are divided into two types. The programmable logic device and field programmable gate array. Programmable logic device is a standard IC?s that are available in standard configurations. The important features of PLD?s are:
• The designing turnaround time is faster. • No customized mask layers or logic cells. The simplest type of programmable IC is a Read only memory (ROM). The most common types of ROM are: • Programmable ROM • Electrically programmable ROM • Electrically Erasable PROM. • Mask Programmable ROM Field programmable gate array is similar to PLD. The only difference between these two is that the FPGA is more complex and larger. The features of a FPGA are: • The mask layers are not customized. • Turnaround time for designing is around few hours. • Programmable I/O cells surround the core.
The Cell library plays a very important role in ASIC design. Each cell in an ASIC cell library must contain the following: • A physical Layout • HDL Model • Timing Model • Routing Model The main advantage of ASIC is that it?s been created for a specific application and is been optimized for the same application. ASIC?s also benefit from the fact that their manufacturing time can be optimized due to fixed application usage. The two disadvantages of ASIC?s are : Long design cycle which includes circuit design and manufacturing process set up. This results in high cost. ASIC industry provides career openings for application engineers, ASIC designers and system engineers. These engineers are trained on VLSI design, peripherals, web enabled devices, modeling, system level simulation and testing. These professionals also help the client companies in development of their new products or redesigning a old product. ASIC market has become more competitive as more number of companies have entered the consumer and electronics market.
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